We will now be looking at how transistors can be combined to perform the very simplest types of information processing or computations. These computations are those of Boolean Logic (and, or, not, not and, etc.). The general term used here it "logic" and these elementary computations are called "logic gates" or "gates" for short. You will see what this means more precisely below.

- Transistor review: nMOS and pMOS
- The simplest gate: inverter or NOT gate
- The NAND gate
- The NOR gate
- All the basic logic gates

### Transistor review: nMOS and pMOS

nMOSFET | pMOSFET |

You can review the detailed behavior of a MOSFET transistor but a brief operational summary follows. For logic purposes, a transistor is a device that acts like a switch: by applying an appropriate high or voltage to it, you can make it act highly conducting ("on") or highly resistive/non-conducting ("off"). Mechanical switches are familiar to all of us: a typical light switch allows one to decide to turn a light on or off by moving a mechanical button and it has only two states; what moving the button does it allow or disallow a current to flow. Transistors are two-state switches in the same sense in that they can allow a current to flow (or not) except that the control is not mechanical but also electrical. This seems like a small difference but in fact is an important distinction: transistors are all electrical (control and output are all electrical) so the output of one transistor can control the input of the next one. By wiring up a large number of transistors appropriately, one can perform complex computations.

On the right you see a schematic representation of a MOSFET transistor, something that is drain on a circuit diagram. The device is controlled by placing a high or low voltage on the Gate (what is shown is a wire that connects to the gate itself). What is controlled is the conductivity between the Source and Drain:

- When the MOSFET is on, the resistance between source and drain is very low and a current flows easily between them or equivalently the voltage difference between them is very small.
- When the MOSFET is off, the resistance is very large between source and drain, very little current flows between them, and their voltages are decoupled from each other.

There are actually two flavors of MOSFETs: nMOSFET (or nMOS) and pMOSFET (or pMOS) which simply refers to the arrangement of n-type and p-type semiconducting materials in the MOSFET transistor. The two behave oppositely with respect to the gate voltage:

- For nMOS, high gate voltage turns it on and low gate voltage turns it off.
- For pMOS, high gate voltage turns it off and low gate voltage turns it on.

The symbols for nMOS and pMOS are very similar except a little circle is placed by the gate to show it is pMOS. The above shows the two symbols side by side.

At this point, you can appreciate how MOSFETs can be used as switches. But it seems like not much has been gained: you choose a gate voltage which decides whether the transistor is on or off, so you have not learned anything you didn't already know. But continue reading and you'll see how combinations of switches allow for computation.

### The simplest gate: inverter or NOT gate

Inverter |

The very simplest possible logical operation is negation or an "inverter" or a "NOT gate" in technical terms. The term "gate" is used to denote a particular circuit element (here built from transistors) that achieves a well-defined purpose. Namely, given a particular set of inputs, it gives a specific output.

The idea of the inverter is that you put in a low or high voltage and get out the opposite: low gives high and high gives low. This can be accomplished by two MOSFETs, one nMOS and one pMOS. The figure on the right shows the arrangement of the MOSFETs. "Vss" just means the source voltage and "Vdd" the drain voltage. "A" labels the input voltage and "Q" the output voltage. Vss and Vdd are help fixed: typically the drain is held at a high constant voltage while the source is set to zero (ground) voltage. As you can see, the source of one transistor has been connected to the drain of the other and we have them in series circuit arrangement.

What does this circuit do, and does it in fact invert? Well, consider putting a high voltage on the input A. This ensures that the nMOS is on and the pMOS is off. So the output Q will be basically connected via very low resistance to the source which is at low (zero) voltage and will thus itself have low voltage; in the meantime, the pMOS being off means that Q and Vdd are basically decoupled and independent. So Q will be low. The converse is also true: when A is low, the nMOS is off and the pMOS is on; Vdd will be basically connected to Q and thus Q will be high while the path from Q to Vss (ground) will be blocked. So Q will be high. Therefore, the circuit does accomplish what it set out to do and it inverts: A high means Q is low and A low means Q is high.

An inverter may seem like a trivial type of device, but it does do the most elementary of computations or logic: it flips high to low or low to high.

### High and low voltages versus binary one and zero

If you are more mathematically inclined or experienced, you probably remember from logic class that one talks more abstractly about ones and zeros and not voltages. The connection is simple: if you say low voltage is zero and high voltage is one, so we have ones and zeros as appropriate for a binary digital device, then an inverter will take an input of 0 and give 1 or take 1 and give 0. Below, we will sometimes use voltages when convenient to describe the action of a circuit at the transistor level, but once we move beyond that we will use ones and zeros: although equivalent, it is a shorter and more convenient description (and also the one used by everyone else!)

In logic, we tend to write input-output relation as a table. For the inverter the table looks like this:

A (input) | Q (output) |
---|---|

0 | 1 |

1 | 0 |

Each input is assigned a column and the last column is the output. The various values the input(s) can take and the resulting output are given in the various rows of the table. Such a table is also called a truth table as it tells you when the output is "true" (1) or "false" (0).

### The NAND gate

To do real logic, one needs more than one input --- this is so that one can combine the multiple inputs and have a more complicated output dependence. The minimum is to have two inputs, and one of the most simple gates is a NAND gate which stands for "not and", i.e. the inverted AND operation. Given two distinct inputs A and B, the output is written "A NAND B" and has the following table

A | B | A NAND B (Out) |
---|---|---|

0 | 0 | 1 |

0 | 1 | 1 |

1 | 0 | 1 |

1 | 1 | 0 |

NAND gate (transistor layout) | NAND gate (physical semiconductor-level layout) |

This says that the output is 1 unless both A and B are 1 in which case it is zero. This is actually a non-trivial computation: the output is the result of a computation on the inputs, in this case the computation is simple and merely checks if both inputs are 1 at the same time.

The MOSFET realization of the NAND gate requires four transistors, two nMOS and to pMOS. The figure on the right shows the arrangement that does the job of creating a NAND function or NAND gate in technical jargon. There are two input voltages A and B (the two different A are really from the same place and thus always at the same voltage but to avoid clutter are shown separately; the same for the two B's). The output is "Out" and we have the source voltage Vss (ground or zero) and the high voltage drains Vdd (both are again connected to the same place). As you can see, in going from drain to source, we have two pMOS in parallel circuit conditions connected then to two nMOS in series.

How does this work? Since the two nMOS are in series, if either of the voltages A or B is low (0), then one (or both) of of the nMOS is (are) off so that the source is disconnected by high resistance from the output; in the meantime at least one of the pMOS is on meaning the drain (high voltage) is essentially connected to the output making for high voltage on Out. Only when both A and B are high (1) do both pMOS turn off and both nMOS turn on so that Out and source (low voltage) are connected and the output is low.

I hope that you can see how a logical computation can be performed in practice with a physical realization through voltages and switches (transistors) --- the physical realization of a mathematical concept. Of course, from a mathematical point of view, any type of physical realization the delivers the input-to-output relation is just as good; but physically, the realizations can be quite different (e.g. transistors versus neurons versus vacuum tubes versus mechanical calculators, etc.) with very different speeds, energy requirements, failure rates, etc.

Before leaving the NAND gate, there is a final point regarding actual layout of the circuitry that embodies the NAND gate at the semiconductor level (i.e. going even a layer below the transistor diagrams). The rightmost figure shows a schematic of this. Following the diagram and its relation to the transistor schematic on its left is somewhat complex, so you can skip this on first reading as it doesn't effect what follows below. What is shown is how various doped layers as well as the source and drain voltage sources and the A and B gate voltages are laid out. A quick look at the diagram doesn't show obviously how four transistors are laid out, so this will take some explaining. First, the highly conducting parts are the blue and green regions. The blue ones are made of metal and are the source (VSS, lower) and drain (VDD, higher). The A and B gates in green are also highly conducting but instead of metal are made from very strongly doped silicon (for practical reasons) --- the doping is so high that these silicon regions have a huge number of carriers and are thus basically metals. The black squares indicate places where actual electrical contact is enforced. The large red swath on top means the entire background layer (behind the blue, green, and yellow stuff) is actually n-type doped silicon. Similarly for the yellow p-type doped swatch below. On top of that are laid rectangles of oppositely doped semiconductors. Then the gates are on top and the metal VDD and VSS connections. So what we are seeing is a top view of a layered structure.

Focusing on the top right region, we see that between VDD contact and Out contact to the yellow p-doped region there is the A gate. The A gate acts on the p-type region right below it and controls the current between the VDD and Out contacts: this is a pMOS! The same structure is also found but with a B gate to the right. The VDD-to-Out connection goes through a region below A or B gates so what we have are two pMOS in parallel, which is what the circuit schematic has drawn. The serial connection of two nMOS to VSS is in the lower part. There we see that to go from Out to VSS, we must go through a n-type material on a p-type base and that we must go under both A and B gates. So this means we have two nMOS in series (controlled by gate A then b as the circuit diagram shows).

As you can see, the actual physical layout of the circuit at the level of semiconductors doesn't have to literally have four separate transistors connected by wires as the transistor-level schematic might imply --- although that would work just as well but be much larger and have lots of duplicated materials. The circuit designer is free to use a layout of semiconductors and wires and gates that minimizes space and makes the fabrication as easy and reliable as possible.

### The NOR gate

NOR gate |

Another possible elementary logic gate (operation) is the NOR gate. It takes two inputs and has one output with the transistor layout shown on the right. As you can see, just like the NAND gate, it has two nMOS and two pMOS transistors but arranged in a different arrangement. Just like the case of the NAND gate above, we can work out the detailed operation of this case by working out the various voltages and resulting behaviors. Here we go: the only way for the output to be connected to VDD is for both pMOS to be on or for both A and B to be low voltage (this also makes both nMOS off so Out is only connected to VDD). If either of A or B is high voltage, then one of the pMOS is off and VDD is disconnected from VDD; at the same time, one of the nMOS is on so Out is connected to VSS via one (or both) transistors.

Translating this behavior into a logic table gives the following:

A | B | A NOR B (Out) |
---|---|---|

0 | 0 | 1 |

0 | 1 | 0 |

1 | 0 | 0 |

1 | 1 | 0 |

### All the basic logic gates

Symbols for logic gates |

There are many types of logic gates one can design with a few transistors. Practically, one doesn't use all the permutations but rather a reasonable subset. Mathematically, it can be proven than any desired logic function (i.e. realizing a particular table that gives output as a function of input choices like the NAND or NOR or NOT cases above) can be built using only NAND or only NOR gates internally --- although the number of gates may be large with complicated connections. In actual circuit design, the gates used and their arrangement does not follow such a rigorous mathematical approach but rather one considers the various possible ways of using different gates to achieve the same function and chooses the one with the smallest number of transistors and complex wiring. Therefore, as you can imagine, efficient circuit design is an art onto itself.

When designing logical functions, it is too cumbersome to draw out the individual transistors making up the circuit so one instead draws the logical gates themselves. There are a few good reasons for doing this: (1) it makes drawing and thinking about the circuit much easier and less cluttered, (2) thinking at transistor level is too detailed and complex to figure out for each possible new circuit, and (3) typically one is putting together basic logic gates to accomplish some computation so one really doesn't care about the transistor function per se but rather about what the gate does. Circuit designers have long used standardized symbols for the logic gates. The figure on the right shows some of the most commons logic gate symbols. The figure has the name of the gate inside for clarity but typical circuit designs only use the symbol and assume the readers knows the nomenclature.

Below are the logic tables for the various gates shown. Although more gates are possible, these are more than sufficient for circuit design and all the examples and principles we discuss below.

A | NOT A |
---|---|

0 | 1 |

1 | 0 |

1 | 1 |

A | B | A AND B |
---|---|---|

0 | 0 | 0 |

0 | 1 | 0 |

1 | 0 | 0 |

1 | 1 | 1 |

A | B | A NAND B |
---|---|---|

0 | 0 | 1 |

0 | 1 | 1 |

1 | 0 | 1 |

1 | 1 | 0 |

A | B | A OR B |
---|---|---|

0 | 0 | 0 |

0 | 1 | 1 |

1 | 0 | 1 |

1 | 1 | 1 |

A | B | A NOR B |
---|---|---|

0 | 0 | 1 |

0 | 1 | 0 |

1 | 0 | 0 |

1 | 1 | 0 |

A | B | A XOR B |
---|---|---|

0 | 0 | 0 |

0 | 1 | 1 |

1 | 0 | 1 |

1 | 1 | 0 |